Memo Review

ECCN Review Recommendation

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Recommended review paths

ECCN Review Recommendation

Classification memo draft prepared for reviewer signoff with evidence and cited review paths.

Draft ECCN Review Memo — ds891 zynq ultrascale plus overview

1. Document Summary

Title: ds891 zynq ultrascale plus overview
Document ID: cmqj7n5rr003pmw10y0murvzu
File name: ds891-zynq-ultrascale-plus-overview.pdf
Generated timestamp: 2026-06-18T08:01:05+00:00
Detected product profile: FPGA / programmable-logic SoC
Profile confidence: high
Profile rationale: Detected from title/filename/top-level references to Zynq UltraScale+ MPSoC, processing system, programmable logic, and SoC features
Disclaimer: Draft for expert review only.

2. Extracted Technical Facts

Product identity

Product Family: Zynq UltraScale+ MPSoC
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: Product-family identity is central here because the document describes an MPSoC family rather than one device ordering code.

Product Name: Zynq UltraScale+ MPSoC
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: Product-name identity helps keep the memo tied to the programmable-logic SoC family under review.

Part Number: Not a single part number - family overview
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: This document is a family overview, so review signoff should use device-specific ordering codes rather than treating the document number as the part number.

Family Overview: true
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: A family overview may omit ordering-code-specific limits, variants, and package-speed-grade details needed for expert review signoff.

Document Number: DS891
Confidence: high
Source snippet: "DS891 (v1.11.1) March 18, 2025 Product Specification"
Why it matters: Document numbers identify the source publication; they should not be substituted for a product part number.

Document Type: Data Sheet
Confidence: medium
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: Document type helps reviewers distinguish a family overview from a device-specific datasheet or ordering-code document.

Manufacturer: AMD
Confidence: high
Source snippet: "of third-party tools and IP providers in combination with the existing AMD PL ecosystem"
Why it matters: Manufacturer identity anchors the review to the vendor’s own part naming, application framing, and qualification language.

Device Type: Processor/SoC
Confidence: medium
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: Device type frames which technical parameters are most relevant in the initial review path.

Product Description: Zynq UltraScale+ MPSoC Data Sheet
Confidence: medium
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: A short product description helps reviewers distinguish the device itself from supporting reference-design or companion-component text.

Profile detection

Detected Product Profile: fpga_programmable_logic_soc
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: The detected profile controls which facts and review paths should be emphasized in the draft memo.

Profile Confidence: high
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: Profile confidence tells the reviewer how strongly the extraction pipeline identified the document type.

Profile Rationale: Detected from title/filename/top-level references to Zynq UltraScale+ MPSoC, processing system, programmable logic, and SoC features
Confidence: high
Source snippet: "Zynq UltraScale+ MPSoC Data Sheet"
Why it matters: Profile rationale explains why the memo is framed as a programmable-logic SoC review rather than an ADC review.

Processing system / CPU

Processor Architecture: 64-bit
Confidence: high
Source snippet: "products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex®-A53 and dual-core Arm"
Why it matters: Processor word width is a processing-system fact for SoC review and must not be treated as converter resolution.

CPU Core: Arm Cortex-A53
Confidence: high
Source snippet: "Arm Cortex-A53 Based Application Dual-core Arm Cortex-R5F Based"
Why it matters: The application CPU core identifies the processing subsystem that may affect the electronics review path.

Core Count: quad-core Cortex-A53
Confidence: high
Source snippet: "Application Processing Unit Quad-core Arm Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point; 32KB/32KB L1 Cache, 1MB L2 Cache"
Why it matters: Core-count language helps reviewers understand the scale of the processing subsystem.

Core Count: dual-core Cortex-A53
Confidence: medium
Source snippet: "Arm Cortex-A53 Based Application Dual-core Arm Cortex-R5F Based"
Why it matters: Family-overview core-count variants should be reviewed against device-specific ordering codes before review signoff.

Real-Time CPU: dual-core Arm Cortex-R5F
Confidence: high
Source snippet: "products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex®-A53 and dual-core Arm Cortex-R5F based processing system (PS) and programmable logic (PL) UltraScale architecture in a single"
Why it matters: A real-time processor subsystem is a material SoC architecture fact for the electronics review path.

GPU: Arm Mali-400
Confidence: medium
Source snippet: "Arm Mali-400 Based GPU  Four 10/100/1000 tri-speed Ethernet MAC"
Why it matters: An integrated GPU is part of the SoC feature set and can affect architecture review.

Cache / TCM: TCM/cache present
Confidence: medium
Source snippet: " Timer and Interrupts o 128KB TCM with ECC (independent for each"
Why it matters: TCM and cache details help distinguish memory-integrity facts from cryptographic features.

Processing System: processing system / PS
Confidence: medium
Source snippet: "Cortex-R5F based processing system (PS) and programmable logic (PL) UltraScale architecture in a single"
Why it matters: Processing-system language establishes that the document covers an integrated SoC, not a standalone peripheral.

Programmable logic / FPGA fabric

Programmable Logic: programmable logic / PL
Confidence: high
Source snippet: "Cortex-R5F based processing system (PS) and programmable logic (PL) UltraScale architecture in a single"
Why it matters: Programmable logic is a defining feature for FPGA/SoC Category 3 electronics review.

PS/PL Integration: PS/PL integration
Confidence: medium
Source snippet: "Cortex-R5F based processing system (PS) and programmable logic (PL) UltraScale architecture in a single"
Why it matters: Integration of processing system and programmable logic is central to FPGA SoC review.

Digital interfaces / high-speed I/O

Ethernet MACs: Four 10/100/1000 tri-speed Ethernet MAC
Confidence: high
Source snippet: "Arm Mali-400 Based GPU  Four 10/100/1000 tri-speed Ethernet MAC"
Why it matters: Ethernet MAC count and speed are relevant high-speed I/O facts for SoC review.

PCIe Interface: PCIe
Confidence: high
Source snippet: " PCI Express — Compliant with PCIe® 2.1 base power domains"
Why it matters: PCIe capability can be relevant to narrower electronics and high-speed interface review.

USB Interface: USB 2.0
Confidence: medium
Source snippet: " Triangle Rate: 0.11 Mtriangles/sec/MHz  Two USB 3.0/2.0 Device, Host, or OTG peripherals"
Why it matters: USB peripheral capability is part of the SoC digital-interface profile.

CAN Interface: CAN
Confidence: medium
Source snippet: "CPU) that can be combined to become 256KB"
Why it matters: CAN peripheral capability is part of the SoC digital-interface profile.

SPI Interface: SPI
Confidence: medium
Source snippet: "rank of 8-, 16-, or 32-bit-wide memories  Two full-duplex SPI ports with three peripheral"
Why it matters: SPI peripheral capability is part of the SoC digital-interface profile.

I2C Interface: I2C
Confidence: medium
Source snippet: "o ONFI3.1 NAND flash with 24-bit ECC  Two master and slave I2C interfaces"
Why it matters: I2C peripheral capability is part of the SoC digital-interface profile.

UART Interface: UART
Confidence: medium
Source snippet: "214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple"
Why it matters: UART peripheral capability is part of the SoC digital-interface profile.

JTAG Interface: JTAG
Confidence: medium
Source snippet: "JTAG Boundary-Scan System Monitor in PL"
Why it matters: JTAG/debug access can matter for device architecture and security review questions.

DisplayPort Interface: DisplayPort
Confidence: high
Source snippet: "and DisplayPort™  Memory Protection Unit (XMPU)"
Why it matters: DisplayPort is a high-speed digital-display interface that may require narrower interface review.

Memory Controller Interface: NAND/eMMC/SD memory interface
Confidence: medium
Source snippet: " ECC support in 64-bit and 32-bit modes  Two SD/SDIO 3.0/eMMC4.51 compliant"
Why it matters: External memory-controller interfaces help characterize the SoC integration profile.

DisplayPort Lane Rate: 1 or 2 lanes at 1.62 Gb/s, 2.7 Gb/s, or 5.4 Gb/s
Confidence: high
Source snippet: "o 1 or 2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s"
Why it matters: DisplayPort lane count and lane rates are concrete high-speed I/O facts for electronics review.

Digital Interface: LVDS
Confidence: medium
Source snippet: " Supports LVCMOS, LVDS, and SSTL"
Why it matters: Digital interface wording helps experts understand how the device connects into a broader digital system.

Security/cryptography indicators

Secure Key Management: Secure hardware-only cryptographic key management
Confidence: high
Source snippet: " Key Management Unit"
Why it matters: Secure key-management features can require security/cryptography review because protected keys may affect functionality and availability analysis.

Secure/Non-Secure Boot: secure and non-secure boot
Confidence: high
Source snippet: "o 1.5, 3.0, and 6.0Gb/s data rates as defined by  Supports secure and non-secure boot modes"
Why it matters: Secure boot and non-secure boot modes can trigger separate security/cryptography review questions.

Cryptographic Algorithm: AES-GCM
Confidence: high
Source snippet: "o 256-bit AES-GCM"
Why it matters: AES-GCM is a named cryptographic algorithm and supports Category 5 Part 2 review questions.

Key Size: 256-bit
Confidence: high
Source snippet: "o 256-bit AES-GCM"
Why it matters: AES key size is relevant to cryptography review and must not be treated as ADC resolution.

Cryptographic Algorithm: SHA-3/384
Confidence: high
Source snippet: "o SHA-3/384"
Why it matters: SHA-3/384 is a named hash algorithm and supports security/cryptography review questions.

Cryptographic Algorithm: RSA 4096
Confidence: high
Source snippet: "o 4096-bit RSA"
Why it matters: RSA 4096 is a named public-key cryptographic function and supports security/cryptography review questions.

Memory/cache integrity

Memory/Cache Integrity: ECC-protected cache
Confidence: high
Source snippet: " AXI Coherency Extension (ACE) instruction and data cache with ECC"
Why it matters: ECC in cache, TCM, or memory context means error-correcting code / memory integrity, not elliptic-curve cryptography.

Memory/Cache Integrity: ECC-protected TCM
Confidence: high
Source snippet: " Timer and Interrupts o 128KB TCM with ECC (independent for each"
Why it matters: ECC in cache, TCM, or memory context means error-correcting code / memory integrity, not elliptic-curve cryptography.

Memory/Cache Integrity: ECC-protected memory/cache
Confidence: high
Source snippet: "o 32KB Level 1, 2-way set-associative  Up to 36Mb on-chip RAM (UltraRAM) with ECC in"
Why it matters: ECC in cache, TCM, or memory context means error-correcting code / memory integrity, not elliptic-curve cryptography.

Peripheral functions

Peripheral ADC: 10-bit, 200 KSPS, up to 17 external inputs
Confidence: high
Source snippet: " 10-bit 200KSPS ADC with up to 17 external inputs"
Why it matters: This is a minor SoC peripheral ADC fact; it should not change the primary product profile to ADC.

GPIO: GPIO
Confidence: medium
Source snippet: "214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; Triple"
Why it matters: GPIO is a general-purpose peripheral fact for the SoC feature profile.

System Monitor: system monitor
Confidence: medium
Source snippet: "o Supports up to two channels System Monitor in PS"
Why it matters: System-monitor language helps identify subordinate monitoring peripherals rather than the primary product type.

Timer: timer
Confidence: medium
Source snippet: "A32/T32 instruction set in 32-bit mode  Timer and Interrupts"
Why it matters: Timer peripherals are part of the SoC feature profile.

Watchdog: watchdog
Confidence: medium
Source snippet: " NEON Advanced SIMD media-processing engine o One watchdog timer"
Why it matters: Watchdog peripherals are part of the SoC feature profile.

Missing/not found facts

Special-environment qualification details were not found in the provided datasheet text. Radiation, military, space, or extended-temperature language matters because specialized design intent can affect the review path.

3. Recommended Review Paths

Category 3 — Category 3 electronics / programmable logic / SoC review path

Confidence: medium
Why it may apply: The document identifies a programmable-logic/SoC family with processing system, programmable logic, high-speed interfaces, and security features. These facts support Category 3 electronics review before fallback classification.
Why it may not apply: The current draft does not encode full CCL thresholds. This is a family overview, so device-specific ordering code and complete specs may be required before review signoff.

Matched facts

Product Family: Zynq UltraScale+ MPSoC
Processor Architecture: 64-bit
CPU Core: Arm Cortex-A53
Real-Time CPU: dual-core Arm Cortex-R5F
Core Count: quad-core Cortex-A53
Core Count: dual-core Cortex-A53
Cache / TCM: TCM/cache present
Memory/Cache Integrity: ECC-protected cache
Memory/Cache Integrity: ECC-protected TCM
Memory/Cache Integrity: ECC-protected memory/cache
Memory Controller Interface: NAND/eMMC/SD memory interface
Programmable Logic: programmable logic / PL
GPU: Arm Mali-400

Citations

Datasheet evidence — product family
Source: Uploaded datasheet text
Citation note: Zynq UltraScale+ MPSoC Data Sheet
Relevance: Product-family identity is central here because the document describes an MPSoC family rather than one device ordering code.

Datasheet evidence — CPU architecture
Source: Uploaded datasheet text
Citation note: products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex®-A53 and dual-core Arm
Relevance: Processor word width is a processing-system fact for SoC review and must not be treated as converter resolution.

Datasheet evidence — CPU architecture
Source: Uploaded datasheet text
Citation note: Arm Cortex-A53 Based Application Dual-core Arm Cortex-R5F Based
Relevance: The application CPU core identifies the processing subsystem that may affect the electronics review path.

Datasheet evidence — Cache / TCM
Source: Uploaded datasheet text
Citation note:  Timer and Interrupts o 128KB TCM with ECC (independent for each
Relevance: TCM and cache details help distinguish memory-integrity facts from cryptographic features.

Datasheet evidence — Memory/Cache Integrity
Source: Uploaded datasheet text
Citation note:  AXI Coherency Extension (ACE) instruction and data cache with ECC
Relevance: ECC in cache, TCM, or memory context means error-correcting code / memory integrity, not elliptic-curve cryptography.

Datasheet evidence — Memory/Cache Integrity
Source: Uploaded datasheet text
Citation note:  Timer and Interrupts o 128KB TCM with ECC (independent for each
Relevance: ECC in cache, TCM, or memory context means error-correcting code / memory integrity, not elliptic-curve cryptography.

Datasheet evidence — Memory/Cache Integrity
Source: Uploaded datasheet text
Citation note: o 32KB Level 1, 2-way set-associative  Up to 36Mb on-chip RAM (UltraRAM) with ECC in
Relevance: ECC in cache, TCM, or memory context means error-correcting code / memory integrity, not elliptic-curve cryptography.

Datasheet evidence — Memory Controller Interface
Source: Uploaded datasheet text
Citation note:  ECC support in 64-bit and 32-bit modes  Two SD/SDIO 3.0/eMMC4.51 compliant
Relevance: External memory-controller interfaces help characterize the SoC integration profile.

Datasheet evidence — programmable logic
Source: Uploaded datasheet text
Citation note: Cortex-R5F based processing system (PS) and programmable logic (PL) UltraScale architecture in a single
Relevance: Programmable logic is a defining feature for FPGA/SoC Category 3 electronics review.

CCL Category 3 electronics / SoC review path
Source: 15 CFR Part 774, Supplement No. 1, Category 3
Citation note: Category 3 electronics review should be considered for a programmable-logic/SoC family with processing-system, programmable logic, high-speed interface, and security-adjacent architecture facts. This draft does not encode final threshold logic.
Relevance: These facts support Category 3 electronics review before fallback classification.

Missing information

Device-specific ordering code, speed grade, package, and complete variant-specific programmable-logic resources.
Current CCL threshold mapping by a qualified reviewer.
Special-environment qualification details were not found in the provided datasheet text. Radiation, military, space, or extended-temperature language matters because specialized design intent can affect the review path.

Reviewer questions

Is this DS891 document a family overview requiring device-specific ordering-code review before review signoff?
Do the programmable-logic and processing-system features require review under Category 3 electronics entries?
Are PCIe, DisplayPort, Ethernet, or other high-speed I/O features relevant to narrower control entries?

Uncertainty flags

multiple_plausible_eccns
requires_engineering_confirmation
limited_regulatory_coverage
missing_key_specs

Category 5 Part 2 — Category 5 Part 2 security/cryptography review path

Confidence: medium
Why it may apply: The document includes secure boot and named cryptographic functions such as AES-GCM, SHA-3/384, and RSA 4096. These may require separate security/cryptography review.
Why it may not apply: The draft does not determine whether functionality is controlled, mass-market eligible, exempt, or otherwise not controlled. A qualified reviewer must evaluate actual cryptographic functionality, availability, and applicable exceptions.

Matched facts

Secure/Non-Secure Boot: secure and non-secure boot
Cryptographic Algorithm: AES-GCM
Cryptographic Algorithm: SHA-3/384
Cryptographic Algorithm: RSA 4096
Key Size: 256-bit
Secure Key Management: Secure hardware-only cryptographic key management

Citations

Datasheet evidence — secure boot
Source: Uploaded datasheet text
Citation note: o 1.5, 3.0, and 6.0Gb/s data rates as defined by  Supports secure and non-secure boot modes
Relevance: Secure boot and non-secure boot modes can trigger separate security/cryptography review questions.

Datasheet evidence — AES-GCM
Source: Uploaded datasheet text
Citation note: o 256-bit AES-GCM
Relevance: AES-GCM is a named cryptographic algorithm and supports Category 5 Part 2 review questions.

Datasheet evidence — SHA-3/384
Source: Uploaded datasheet text
Citation note: o SHA-3/384
Relevance: SHA-3/384 is a named hash algorithm and supports security/cryptography review questions.

Datasheet evidence — RSA 4096
Source: Uploaded datasheet text
Citation note: o 4096-bit RSA
Relevance: RSA 4096 is a named public-key cryptographic function and supports security/cryptography review questions.

Datasheet evidence — Key Size
Source: Uploaded datasheet text
Citation note: o 256-bit AES-GCM
Relevance: AES key size is relevant to cryptography review and must not be treated as ADC resolution.

Datasheet evidence — Secure Key Management
Source: Uploaded datasheet text
Citation note:  Key Management Unit
Relevance: Secure key-management features can require security/cryptography review because protected keys may affect functionality and availability analysis.

Category 5 Part 2 security/cryptography review path
Source: 15 CFR Part 774, Supplement No. 1, Category 5 Part 2
Citation note: Security and cryptography functions such as secure boot, AES-GCM, SHA-3/384, and RSA 4096 may require separate Category 5 Part 2 analysis by a qualified reviewer.
Relevance: This path captures named security facts for expert review of control status, mass-market eligibility, exceptions, and availability.

Missing information

Whether crypto is user-accessible.
Whether mass-market or license exception treatment applies.
Whether implementation details are in a security manual rather than this overview.

Reviewer questions

Do secure boot, AES-GCM, SHA-3/384, or RSA 4096 require separate Category 5 Part 2 analysis?
Is the cryptographic functionality user-accessible, configurable, or limited to boot/authentication functions?
Are implementation details in a separate security manual not captured by this overview?

Uncertainty flags

requires_engineering_confirmation
missing_key_specs
limited_regulatory_coverage

3A991 — General electronics comparison path

Confidence: low
Why it may apply: A broader general-electronics comparison path remains relevant only as fallback after the programmable-logic/SoC and security review paths are evaluated.
Why it may not apply: The document contains specific programmable-logic, processing-system, high-speed I/O, and cryptography facts that should be reviewed under narrower paths before relying on a general fallback comparison.

Matched facts

Product Family: Zynq UltraScale+ MPSoC
Processor Architecture: 64-bit
CPU Core: Arm Cortex-A53
Programmable Logic: programmable logic / PL

Citations

General electronics fallback review
Source: EAR classification comparison workflow
Citation note: A broader general-electronics path should be considered only after the narrower Category 3 electronics review paths are examined and excluded by a qualified reviewer.
Relevance: This is a fallback comparison point only. It should not be treated as the likely answer while narrower Category 3 review paths remain open.

Missing information

Documented reasoning for excluding Category 3 programmable-logic/SoC and Category 5 Part 2 security review paths.
Special-environment qualification details were not found in the provided datasheet text. Radiation, military, space, or extended-temperature language matters because specialized design intent can affect the review path.

Reviewer questions

What documented reasoning supports excluding narrower Category 3 and Category 5 review paths before considering a broader general-electronics comparison?

Uncertainty flags

limited_regulatory_coverage
missing_key_specs
requires_engineering_confirmation

4. Key Uncertainties

limited regulatory coverage
missing key specs
requires engineering confirmation

5. Reviewer Questions

Is this DS891 document a family overview requiring device-specific ordering-code review before review signoff?
Do the programmable-logic and processing-system features require review under Category 3 electronics entries?
Are PCIe, DisplayPort, Ethernet, or other high-speed I/O features relevant to narrower control entries?
Do secure boot, AES-GCM, SHA-3/384, or RSA 4096 require separate Category 5 Part 2 analysis?
Is the cryptographic functionality user-accessible, configurable, or limited to boot/authentication functions?
Are implementation details in a separate security manual not captured by this overview?
What documented reasoning supports excluding narrower Category 3 and Category 5 review paths before considering a broader general-electronics comparison?

6. ECCN Review Recommendation

Substrata recommends reviewing Category 3 electronics / programmable-logic / SoC paths and Category 5 Part 2 security/cryptography paths based on the extracted datasheet evidence.
Because this is a family overview, a qualified reviewer should confirm the exact ordering code, speed grade, package, security functionality, and applicable CCL threshold mapping.

7. Review State

Status: Needs human review
Reviewer: Unassigned
Note: No reviewer note recorded yet.